Custom SSDT Table for EIST on my Laptop

WARNING

DANGER WILL ROBINSON DANGER

This procedure is making low level changes to the functionality of your hardware and software. Munging this up can do 'bad things' to your system. You have been warned.

Step 1

Read the Warning section 2-3 more times. You really need to understand what is going on here

Background

My laptop (an Alienware Area51-M 7700) shipped with a P4 530. After 3 years, I replaced it with a P4 630, for 64bit support. The problem being, the bios does not support the new CPU's EIST functionality. Really, the only problem here is that the bios does not announce that the CPU has the capabilities, and as such, the acpi-cpufreq module does not use them.

There are multiple ways to attack this problem. I've chosen the most educating one for me.

References

This is the list of sites I referenced during this project:

System Specific References

Utilities needed:

Overview on Relevant DSDT/SSDT table Entries

The only Scope we're worried about in this is the \_PR scope, where the original DSDT table defined the Processor. I believe that this can safely be ported to the \_SB scope, but have not researched that thouroughly. Inside the \_PR scope, we have 2 Processors defined, the Main (Real) CPU and the logical HT CPU. For EIST to work, these CPUs need to have P-States defined, as well as their helper functions:

On top of the P-State options, I'm also adding C-States to the SSDT so that C2 Sleep, etc are supported.

Dumping my SSDT/DSDT tables

During my preparation for this project, I discovered that my DSDT table is also buggy. I figured I'd fix that as well.

The relevant dmesg data about my Bios:

ACPI: RSDP 00000000000f6c40 00014 (v00 PTLTD )
ACPI: RSDT 000000005fea937d 0003C (v01 PTLTD    RSDT   06040000  LTP 00000000)
ACPI: FACP 000000005feaee21 00074 (v01 Clevo           06040000 PTL  00000003)
ACPI: DSDT 000000005fea93b9 05A68 (v01  INTEL GRANTSDL 06040000 MSFT 0100000E)
ACPI: FACS 000000005feaffc0 00040
ACPI: APIC 000000005feaee95 00068 (v01 PTLTD  ? APIC   06040000  LTP 00000000)
ACPI: APIC 000000005feaeefd 00068 (v01 PTLTD  ? APIC   06040000  LTP 00000000)
ACPI: BOOT 000000005feaef65 00028 (v01 PTLTD  $SBFTBL$ 06040000  LTP 00000001)
ACPI: MCFG 000000005feaef8d 0003C (v01 PTLTD    MCFG   06040000  LTP 00000000)
ACPI: SSDT 000000005feaefc9 00037 (v01 PTLTD  ACPIHT   06040000  LTP 00000001)
ACPI: BIOS bug: multiple APIC/MADT found, using 0
ACPI: If "acpi_apic_instance=2" works better, notify linux-acpi@vger.kernel.org
ACPI: Local APIC address 0xfee00000

Notice, the DSDT table lists MSFT as the compiler used. The microsoft ASL compiler is 'lenient' on what it considers valid code. Dumping the DSDT table, then decompiling and recompiling with iasl showed that it was not 'clean'.

boatanchor /usr/src/DSDT $ sudo cat /sys/firmware/acpi/tables/DSDT > dsdt.dat
boatanchor /usr/src/DSDT $ iasl -d dsdt.dat

Intel ACPI Component Architecture
AML Disassembler version 20091013 [Oct 25 2009]
Copyright (C) 2000 - 2009 Intel Corporation
Supports ACPI Specification Revision 4.0

Loading Acpi table from file dsdt.dat
Acpi table [DSDT] successfully installed and loaded
Pass 1 parse of [DSDT]
Pass 2 parse of [DSDT]
Parsing Deferred Opcodes (Methods/Buffers/Packages/Regions)
............................................................................................................................................................................................................................................................................................................
Parsing completed
Disassembly completed, written to "dsdt.dsl"
boatanchor /usr/src/DSDT $ iasl -tc dsdt.dsl

Intel ACPI Component Architecture
ASL Optimizing Compiler version 20091013 [Oct 25 2009]
Copyright (C) 2000 - 2009 Intel Corporation
Supports ACPI Specification Revision 4.0

dsdt.dsl  2177:                     LV34,   1
Error    4028 -                        ^ Access width of Field Unit extends beyond region limit

dsdt.dsl  3347:                     Field (RAM, AnyAcc, Lock, Preserve)
Error    4075 -                              ^ Host Operation Region requires ByteAcc access

dsdt.dsl  4376:                 Field (IDE1, DWordAcc, NoLock, Preserve)
Error    4027 -                           ^ Access width is greater than region size

dsdt.dsl  4378:                     MAP,    8,
Error    4028 -                       ^ Access width of Field Unit extends beyond region limit

dsdt.dsl  4380:                     PCS,    8
Error    4028 -                       ^ Access width of Field Unit extends beyond region limit

dsdt.dsl  5388:     Method (_WAK, 1, NotSerialized)
Warning  1080 -                ^ Reserved method must return a value (_WAK)

ASL Input:  dsdt.dsl - 5616 lines, 210773 bytes, 2542 keywords
Compilation complete. 5 Errors, 1 Warnings, 0 Remarks, 617 Optimizations

So... before attacking adding EIST to the SSDT table, I'm going to fix the DSDT table.

Fixing the DSDT

I followed similar steps to those done in the Gentoo forums thread, a summary of solutions to the problems:

here's my diff:

boatanchor /usr/src/DSDT $ diff -u DSDT.dsl dsdt.dsl
--- DSDT.dsl    2010-04-15 09:25:22.000000000 -0400
+++ dsdt.dsl    2010-04-15 09:59:28.000000000 -0400
@@ -16,7 +16,7 @@
  *     Compiler ID      "MSFT"
  *     Compiler Version 0x0100000E (16777230)
  */
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "INTEL", "GRANTSDL", 0x06040000)
+DefinitionBlock ("dsdt.aml", "DSDT", 1, "INTEL", "GRANTSDL", 0x06040000)
 {
     OperationRegion (Z000, SystemIO, 0xB2, 0x01)
     Field (Z000, ByteAcc, NoLock, Preserve)
@@ -2156,7 +2156,7 @@
                     }
                 }

-                OperationRegion (GPOX, SystemIO, 0x1180, 0x3B)
+                OperationRegion (GPOX, SystemIO, 0x1180, 0x3C)
                 Field (GPOX, DWordAcc, NoLock, Preserve)
                 {
                             Offset (0x07),
@@ -3344,7 +3344,7 @@
                             )
                     })
                     OperationRegion (RAM, EmbeddedControl, 0x00, 0xFF)
-                    Field (RAM, AnyAcc, Lock, Preserve)
+                    Field (RAM, ByteAcc, Lock, Preserve)
                     {
                         NMSG,   8,
                         SLED,   5,
@@ -4372,7 +4372,7 @@
             Device (IDE1)
             {
                 Name (_ADR, 0x001F0002)
-                OperationRegion (IDE1, PCI_Config, 0x90, 0x03)
+                OperationRegion (IDE1, PCI_Config, 0x90, 0x04)
                 Field (IDE1, DWordAcc, NoLock, Preserve)
                 {
                     MAP,    8,
@@ -5412,6 +5412,7 @@
         {
             Notify (\_SB.PWRB, 0x02)
         }
+       Return(Package(0x02){0x00, 0x00})
     }

     Scope (\_SB)

Now recompiling:

boatanchor /usr/src/DSDT $ iasl -tc dsdt.dsl

Intel ACPI Component Architecture
ASL Optimizing Compiler version 20091013 [Oct 25 2009]
Copyright (C) 2000 - 2009 Intel Corporation
Supports ACPI Specification Revision 4.0

ASL Input:  dsdt.dsl - 5617 lines, 210809 bytes, 2543 keywords
AML Output: dsdt.aml - 21632 bytes, 718 named objects, 1825 executable opcodes

Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 619 Optimizations

and I have a new dsdt.hex for my bios. Let's install it and reboot!

Installing the DSDT

Again, I'm building on other people's work here. I'm going to create a folder in /etc for my DSDT and SSDT files:

boatanchor /usr/src/DSDT $ sudo mkdir /etc/SDT
boatanchor /usr/src/DSDT $ sudo cp dsdt.hex /etc/SDT

And add the dsdt.aml to my kernel:

Kernel Settings:

 Device Drivers -> 
   Generic Driver Options -> 
     [ ] Select only drivers that don't need compile-time external firmware

 Power management and ACPI options -> 
   ACPI (Advanced Configuration and Power Interface) Support -> 
     (/etc/SDT/dsdt.hex) Custom DSDT Table file to include

Rebuild the kernel, install, and reboot.

Woohoo! Tainted kernel with clean DSDT table:

ACPI: RSDP 00000000000f6c40 00014 (v00 PTLTD )
ACPI: RSDT 000000005fea937d 0003C (v01 PTLTD    RSDT   06040000  LTP 00000000)
ACPI: FACP 000000005feaee21 00074 (v01 Clevo           06040000 PTL  00000003)
ACPI: Override [DSDT-GRANTSDL], this is unsafe: tainting kernel
Disabling lock debugging due to kernel taint
ACPI: DSDT @ 0x000000005fea93b9 Table override, replaced with:
ACPI: DSDT ffffffff81412690 05480 (v01  INTEL GRANTSDL 06040000 INTL 20091013)
ACPI: FACS 000000005feaffc0 00040
ACPI: APIC 000000005feaee95 00068 (v01 PTLTD  ? APIC   06040000  LTP 00000000)
ACPI: APIC 000000005feaeefd 00068 (v01 PTLTD  ? APIC   06040000  LTP 00000000)
ACPI: BOOT 000000005feaef65 00028 (v01 PTLTD  $SBFTBL$ 06040000  LTP 00000001)
ACPI: MCFG 000000005feaef8d 0003C (v01 PTLTD    MCFG   06040000  LTP 00000000)
ACPI: SSDT 000000005feaefc9 00037 (v01 PTLTD  ACPIHT   06040000  LTP 00000001)
ACPI: BIOS bug: multiple APIC/MADT found, using 0
ACPI: If "acpi_apic_instance=2" works better, notify linux-acpi@vger.kernel.org

Multiple APIC Tables

Next, we'll check out the APIC error, see if it's actually a problem for us:

boatanchor /usr/src/DSDT $ sudo cat /sys/firmware/acpi/tables/APIC1 > apic1.dat
boatanchor /usr/src/DSDT $ sudo cat /sys/firmware/acpi/tables/APIC2 > apic2.dat
boatanchor /usr/src/DSDT $ iasl -d apic1.dat

Intel ACPI Component Architecture
AML Disassembler version 20091013 [Oct 25 2009]
Copyright (C) 2000 - 2009 Intel Corporation
Supports ACPI Specification Revision 4.0

Loading Acpi table from file apic1.dat
Acpi Data Table [APIC] decoded, written to "apic1.dsl"
boatanchor /usr/src/DSDT $ iasl -d apic2.dat

Intel ACPI Component Architecture
AML Disassembler version 20091013 [Oct 25 2009]
Copyright (C) 2000 - 2009 Intel Corporation
Supports ACPI Specification Revision 4.0

Loading Acpi table from file apic2.dat
Acpi Data Table [APIC] decoded, written to "apic2.dsl"
boatanchor /usr/src/DSDT $ diff -u apic1.dsl apic2.dsl
--- apic1.dsl   2010-04-15 10:36:07.000000000 -0400
+++ apic2.dsl   2010-04-15 10:36:13.000000000 -0400
@@ -2,7 +2,7 @@
  * Intel ACPI Component Architecture
  * AML Disassembler version 20091013
  *
- * Disassembly of apic1.dat, Thu Apr 15 10:36:07 2010
+ * Disassembly of apic2.dat, Thu Apr 15 10:36:13 2010
  *
  * ACPI Data Table [APIC]
  *

As we can see from the diff, they're identical. No need to worry about that warning.

Dumping the SSDT Table

Now we dump the SSDT table, and recompile it once to verify it's good.

boatanchor /usr/src/DSDT $ sudo cat /sys/firmware/acpi/tables/SSDT > ssdt.dat
boatanchor /usr/src/DSDT $ iasl -d ssdt.dat

Intel ACPI Component Architecture
AML Disassembler version 20091013 [Oct 25 2009]
Copyright (C) 2000 - 2009 Intel Corporation
Supports ACPI Specification Revision 4.0

Loading Acpi table from file ssdt.dat
Acpi table [SSDT] successfully installed and loaded
Pass 1 parse of [SSDT]
Pass 2 parse of [SSDT]
Parsing Deferred Opcodes (Methods/Buffers/Packages/Regions)

Parsing completed
Disassembly completed, written to "ssdt.dsl"
boatanchor /usr/src/DSDT $ iasl -tc ssdt.dsl

Intel ACPI Component Architecture
ASL Optimizing Compiler version 20091013 [Oct 25 2009]
Copyright (C) 2000 - 2009 Intel Corporation
Supports ACPI Specification Revision 4.0

ASL Input:  ssdt.dsl - 28 lines, 642 bytes, 2 keywords
AML Output: ssdt.aml - 55 bytes, 2 named objects, 0 executable opcodes

Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 0 Optimizations

Yep, it compiled cleanly.... but at only 28 lines, it would have been tough to screw up. My impressive SSDT table (from bios):

/*
 * Intel ACPI Component Architecture
 * AML Disassembler version 20091013
 *
 * Disassembly of ssdt.dat, Thu Apr 15 10:55:11 2010
 *
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x00000037 (55)
 *     Revision         0x01
 *     Checksum         0x23
 *     OEM ID           "PTLTD "
 *     OEM Table ID     "ACPIHT  "
 *     OEM Revision     0x06040000 (100925440)
 *     Compiler ID      " LTP"
 *     Compiler Version 0x00000001 (1)
 */
DefinitionBlock ("ssdt.aml", "SSDT", 1, "PTLTD ", "ACPIHT  ", 0x06040000)
{
    Scope (_PR)
    {
        Processor (CPU1, 0x01, 0x00001010, 0x06) {}
    }
}

Wow... just wow.

This SSDT only contains the entry for the HT CPU. Yep, you read that correctly. It being titled 'ACPIHT' probably should have given that away, but it doesn't matter, at least there's not much we have to deal with in it.

Now onto the can-o-worms... a custom SSDT. First I'm going to just test my default SSDT overriding the BIOS SSDT. Per the lesswatts page, we need to merge the DSDT and SSDT tables into 1 override:

boatanchor /usr/src/DSDT $ cat dsdt.dsl ssdt.dsl > dsdt_ssdt.dsl
boatanchor /usr/src/DSDT $ iasl -tc ./dsdt_ssdt.dsl

Intel ACPI Component Architecture
ASL Optimizing Compiler version 20091013 [Oct 25 2009]
Copyright (C) 2000 - 2009 Intel Corporation
Supports ACPI Specification Revision 4.0

./dsdt_ssdt.dsl  5634: DefinitionBlock
Error    4095 -                      ^ syntax error, unexpected PARSEOP_DEFINITIONBLOCK, expecting $end

ASL Input:  ./dsdt_ssdt.dsl - 5635 lines, 211307 bytes, 2543 keywords
Compilation complete. 1 Errors, 0 Warnings, 0 Remarks, 619 Optimizations

Off to a rocky start... merging the two outright did not work. Turns out, we need to inject the contents of the SSDT block into the DSDT block.

boatanchor /usr/src/DSDT $ diff -u dsdt_ssdt.orig dsdt_ssdt.dsl
--- dsdt_ssdt.orig      2010-04-15 11:06:52.000000000 -0400
+++ dsdt_ssdt.dsl       2010-04-15 11:06:41.000000000 -0400
@@ -5611,7 +5611,7 @@
             Store (\_SB.PCI0.LPC0.EC.ADP, Local0)
         }
     }
-}
+// }

 /*
  * Intel ACPI Component Architecture
@@ -5631,8 +5631,8 @@
  *     Compiler ID      " LTP"
  *     Compiler Version 0x00000001 (1)
  */
-DefinitionBlock ("ssdt.aml", "SSDT", 1, "PTLTD ", "ACPIHT  ", 0x06040000)
-{
+// DefinitionBlock ("ssdt.aml", "SSDT", 1, "PTLTD ", "ACPIHT  ", 0x06040000)
+// {
     Scope (_PR)
     {
         Processor (CPU1, 0x01, 0x00001010, 0x06) {}

Rebuild the kernel, and reboot with the "acpi_no_auto_ssdt" kernel command line option. That kernel option tells the acpica system to ignore the SSDT tables that are found in the bios reported ACPI table, and instead, load whatever we tell it to.

At this point, we've overridden the Bios' SSDT table with a dump of it, now it's time to add the EIST information to the DSDT table. Some things I learned:

First things first, we need to come up with a CPU-Freqeuncy List, and convert those values to FIDs.

In the case of my CPU, it barely supports EIST (but still better than p4-clockmod), so it supports:

That's it. The FID values are from the

So I just need 2 C States for my CPU and HT CPU. Here's my DSDT+SSDT Diff:

--- dsdt_ssdt.orig      2010-04-15 11:06:52.000000000 -0400
+++ dsdt_ssdt.dsl       2010-04-16 13:03:59.000000000 -0400
@@ -59,7 +59,7 @@

     Scope (_PR)
     {
-        Processor (CPU0, 0x00, 0x00001010, 0x06) {}
+        Processor (\_PR.CPU0, 0x00, 0x00001010, 0x06) {}
     }

     Scope (_SB)
@@ -5611,31 +5611,108 @@
             Store (\_SB.PCI0.LPC0.EC.ADP, Local0)
         }
     }
-}

-/*
- * Intel ACPI Component Architecture
- * AML Disassembler version 20091013
- *
- * Disassembly of ssdt.dat, Thu Apr 15 10:55:11 2010
- *
- *
- * Original Table Header:
- *     Signature        "SSDT"
- *     Length           0x00000037 (55)
- *     Revision         0x01
- *     Checksum         0x23
- *     OEM ID           "PTLTD "
- *     OEM Table ID     "ACPIHT  "
- *     OEM Revision     0x06040000 (100925440)
- *     Compiler ID      " LTP"
- *     Compiler Version 0x00000001 (1)
- */
-DefinitionBlock ("ssdt.aml", "SSDT", 1, "PTLTD ", "ACPIHT  ", 0x06040000)
-{
+    /*
+       My Custom Work
+     */
+    // Register the HT Processor
     Scope (_PR)
     {
-        Processor (CPU1, 0x01, 0x00001010, 0x06) {}
+        Processor (\_PR.CPU1, 0x01, 0x00001010, 0x06) {}
+    }
+
+    // Main CPU's EIST DSDT Stuff
+    Scope (\_PR.CPU0)
+    {
+        // Performance Present Capabilities 8.4.4.3
+        Method (_PPC, 0, NotSerialized)
+        {
+           Store ("PPC-CPU0", Debug)
+            Return (Zero)
+        }
+
+       // Performance Control (ACPI spec chapter 8.4.4.1)
+        Method (_PCT, 0, NotSerialized)
+        {
+           Store ("PCT-CPU0", Debug)
+           Return (Package (0x02)
+               {
+                  ResourceTemplate ()
+                   {
+                       Register (FFixedHW, // PERF_CTL
+                           0x10,              // Bit Width
+                           0x00,               // Bit Offset
+                           0x0000000000000199, // Address
+                           ,)
+                   },
+
+                   ResourceTemplate ()
+                   {
+                       Register (FFixedHW, // PERF_STATUS
+                           0x10,               // Bit Width
+                           0x00,    // Bit Offset
+                           0x0000000000000198, // Address
+                           ,)
+                   }
+               })
+        }
+        // Performance Supported States(ACPI spec chapter 8.4.4.2)
+        Method (_PSS, 0, NotSerialized)
+        {
+           Store ("PSS-CPU0", Debug)
+            Return (Package (0x02)
+            {
+               Package (0x06){3000, 84000, 10, 10, 0x00000F2D, 0x00000F2D},
+              Package (0x06){2800, 80000, 10, 10, 0x00000E1C, 0x00000E1C}
+            })
+        }
+    }
+
+    // HT CPU's EIST DSDT Stuff
+    Scope (\_PR.CPU1)
+    {
+        // Performance Present Capabilities 8.4.4.3
+        Method (_PPC, 0, NotSerialized)
+        {
+           Store ("PPC-CPU1", Debug)
+            Return (0x00)
+        }
+
+       // Performance Control (ACPI spec chapter 8.4.4.1)
+        Method (_PCT, 0, NotSerialized)
+        {
+           Store ("PCT-CPU1", Debug)
+           Return (Package (0x02)
+            {
+               ResourceTemplate ()
+               {
+                   Register (FFixedHW, // PERF_CTL
+                    0x10,              // Bit Width
+                    0x00,               // Bit Offset
+                    0x0000000000000199, // Address
+                    ,)
+               },
+
+               ResourceTemplate ()
+               {
+                    Register (FFixedHW, // PERF_STATUS
+                    0x10,               // Bit Width
+                    0x00,    // Bit Offset
+                    0x0000000000000198, // Address
+                    ,)
+               }
+            })
+        }
+        // Performance Supported States(ACPI spec chapter 8.4.4.2)
+        Method (_PSS, 0, NotSerialized)
+        {
+           Store ("PSS-CPU1", Debug)
+            Return (Package (0x02)
+            {
+               Package (0x06){3000, 84000, 10, 10, 0x00000F2D, 0x00000F2D},
+               Package (0x06){2800, 80000, 10, 10, 0x00000E1C, 0x00000E1C}
+           })
+        }
     }
 }

And that does it. There's a TONNE of handwaiving in there for now.. Specifically, I don't show how to calculate any of the values in the _PSS method.... once I get a better understanding of that, I'll include it. Now the acpi-cpufreq module will load, and allow the transitions to take effect. One problem: The HT and Real CPUs are being changed independantly...

The _PSD Field

A quick change to each Processor () entry to fix EIST+HT. This must exist in each Processor () macro.

--- dsdt_ssdt.orig      2010-04-15 11:06:52.000000000 -0400
+++ dsdt_ssdt.dsl       2010-04-16 15:59:21.000000000 -0400
@@ -59,7 +59,10 @@

     Scope (_PR)
     {
-        Processor (CPU0, 0x00, 0x00001010, 0x06) {}
+        Processor (\_PR.CPU0, 0x00, 0x00001010, 0x06)
+        {
+           Name (_PSD, Package (0x05){0x05,0x00,0x00,0xFC,0x02})
+        }
     }

     Scope (_SB)

What that does is defines the P-State Dependancy for CPU0 (identical entry needed for CPU1), so that the acpi-cpufreq module knows that changing one CPU's P-State changes both.

Adding C-States

This notebook is based off of the intel ICH6 chipset. According to the spec, all ICH6 chipsets support C1 and C2

C1 is easy to figure out, just adding a generic entry:

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x000, 0x01,)},1,0x10,35000},

did it. The 3500 and 0x10 are 'voodoo' numbers right now. I don't have CPU Specific power draw or transition latency stats for this CPU. I need to figure out how to get those numbers.

Next up, C2. This was a little trickier, requiring I dive into the ICH6 chipset specs. According to 10.8.3.6 (Level 2 Register), a read of 8 bits from PM_BASE + 0x04 would enable C2. PM_Base is available at 0x1010 in my system so this entry:

Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x0, 0x1014,)},2,0x10,25000},

Should enable C2. Tested, it does.

Summary

C-States and P-States working!

boatanchor /usr/src/DSDT $ cat /proc/acpi/processor/CPU0/power
active state:            C0
max_cstate:              C8
maximum allowed latency: 2000000000 usec
states:
    C1:                  type[C1] promotion[--] demotion[--] latency[016] usage[00465393] duration[00000000000000000000]
    C2:                  type[C2] promotion[--] demotion[--] latency[016] usage[10136105] duration[00000000023985252124]
boatanchor /usr/src/DSDT $ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
3000000 2800000

Update

Turns out, my system supports C3 and C4 as well:

cat /proc/acpi/processor/CPU0/power
active state:            C0
max_cstate:              C8
maximum allowed latency: 2000000000 usec
states:
    C1:                  type[C1] promotion[--] demotion[--] latency[001] usage[00000003] duration[00000000000000000000]
    C2:                  type[C2] promotion[--] demotion[--] latency[001] usage[00198462] duration[00000000000440100406]
    C3:                  type[C3] promotion[--] demotion[--] latency[085] usage[00030230] duration[00000000000000967501]
    C4:                  type[C3] promotion[--] demotion[--] latency[150] usage[98901022] duration[00000000003164834168]

Still working on C1E/Mwait...

C1E/MWAIT works

I can't really say 'why' it works now, I didn't change anything. I updated my kernel and now it works...

My DSDT File

here's the Processor definition from my DSDT now. it has C1-C4 and P1-P2 working for my p4 630:

        Processor (CPU0, 0x00, 0x00001010, 0x06)
        {
            Method (_PPC, 0, NotSerialized)
            {
                Return (Zero)
            }

            Method (_PDC, 0, NotSerialized)
            {
            }}

            Name (_CST, Package (0x05)
            {
                0x04,
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    },

                    One,
                    One,
                    0x03E8
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (SystemIO,
                            0x08,               // Bit Width
                            0x00,               // Bit Offset
                            0x0000000000001014, // Address
                            ,)
                    },

                    0x02,
                    One,
                    0x01F4
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (SystemIO,
                            0x08,               // Bit Width
                            0x00,               // Bit Offset
                            0x0000000000001015, // Address
                            ,)
                    },

                    0x03,
                    0x55,
                    0xFA
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (SystemIO,
                            0x08,               // Bit Width
                            0x00,               // Bit Offset
                            0x0000000000001016, // Address
                            ,)
                    },

                    0x03,
                    0x96,
                    0x64
                }
            })
            Name (_PSS, Package (0x02)
            {
                Package (0x06)
                {
                    0x0BB8,
                    0x00014820,
                    0x0A,
                    0x0A,
                    0x0F2D,
                    0x0F2D
                },

                Package (0x06)
                {
                    0x0AF0,
                    0x000130B0,
                    0x0A,
                    0x0A,
                    0x0E1C,
                    0x0E1C
                }
            })
        }

Other/P4EISTSSDT (last edited 2010-05-05 14:47:55 by PatErley)